1. Technical Field
The present invention relates to a semiconductor device including an FET and a non-volatile memory, and a method of manufacturing the semiconductor device.
2. Related Art
Japanese Unexamined Patent Publication No. 2006-269586 discloses a semiconductor element having a comb-shape gate electrode.
Japanese Unexamined Patent Publication Nos. 2005-353106 and 2007-157183 disclose a method of forming a non-volatile memory without adding any process to a general logic CMOS forming process by positively deteriorating hot carriers to trap charges below a side wall.
Hereinafter, the problems to be solved by the invention will be described with reference to the accompanying drawings.
As shown in FIGS. 7A and 7B, an FET forming region including a first gate insulating film 122 and a first gate electrode 112 is provided on a first diffusion layer 118 surrounded by an element isolation region 111 on a substrate 110, and a non-volatile memory forming region including a second gate insulating film 124 and a second gate electrode 114 is provided on a second diffusion layer 120 surrounded by the element isolation region 111. FIG. 7A is a top view schematically illustrating the FET forming region and the non-volatile memory forming region of the semiconductor device, and FIG. 7B is cross-sectional views taken along the lines A-A′ and D-D′.
Then, a pair of extension regions 132 and pocket regions 133 are formed in the FET forming region of the substrate using the first gate electrode 112 and a resist film formed so as to cover the non-volatile memory forming region as a mask. Then, the resist film formed so as to cover the non-volatile memory forming region is removed.
Then, as shown in FIGS. 8A and 8B, a first side wall 140 is formed on the side wall of the first gate electrode 112, and a second side wall 143 is formed on the side wall of the second gate electrode 114. The first side wall 140 includes a first insulating film 136 and a second insulating film 138. The second side wall 143 includes a first insulating film 141 and a second insulating film 142. FIG. 8A is a top view schematically illustrating the FET forming region and the non-volatile memory forming region of the semiconductor device, and FIG. 8B is cross-sectional views taken along the lines A-A′ and D-D′.
Then, impurities are implanted using the first gate electrode 112 and the first side wall 140, and the second gate electrode 114 and the second side wall 143 as a mask. In this way, a pair of first source/drain regions 144 is formed on both sides wall of the first side wall 140 in the vicinity of the surface of the substrate, and a pair of second source/drain regions 146 is formed on both sides of the second side wall 143 in the vicinity of the surface of the substrate.
Then, the impurities in the first source/drain regions 144 and the second source/drain regions 146 are activated by annealing (FIG. 9).
According to this method, since the resist film covers the non-volatile memory forming region, it is difficult to form an extension region and a pocket region in the non-volatile memory forming region. Therefore, in the non-volatile memory forming region, the intensity of an electric field in the horizontal direction is increased, and hot carriers are more likely to be generated. As a result, it is possible to trap charges below the second side wall 143.
However, as shown in FIG. 9, when the extension region is not formed in the non-volatile memory forming region, the ends of the second source/drain regions 146 are not formed immediately below the second side wall 143, but are formed immediately below the second gate electrode 114.
Since the electric field is strongest at the ends of the second source/drain regions 146, the largest amount of hot carrier is generated at the ends. Therefore, when the ends of the second source/drain regions 146 are formed immediately below the second gate electrode 114, many hot electrons are trapped by a gate oxide film, and it is impossible to effectively trap electrons below the second side wall 143.
In recent years, as the size of the semiconductor device has been reduced, the size of the side wall has been significantly reduced.